1. Field of the Invention
This invention relates to a semiconductor integrated circuit device, and more particularly to a high density integrated circuit device consisting of silicon gate MOS FETs (Metal Oxide Semiconductor Field Effect Transistors).
2. Description of the Prior Art
Semiconductor integrated circuit devices utilizing silicon gate MOS FETs in which the gate electrode is constituted of a conductive polycrystalline silicon layer are well-known. This integrated circuit device has some advantages, as compared with the known aluminium gate MOS integrated circuit device, such as the fact that multi-layer wiring can be easily employed. To manufacture this integrated circuit device, a technique of forming the wiring layer and the functional elements simultaneously known as the direct contact method is used.
In the silicon gate MOS integrated circuit device referred to above, the delay of transmission signals has become an important problem. This signal delay is caused by the high resistance of the wiring interconnecting the MOS transistors. The length of the gate electrode is not important, because its length is very much shorter than that of the interconnecting wiring. To reduce the resistance, that is, to raise the conductivity of the polycrystalline layer, one could diffuse a heavy impurity concentration therein. However, there is a limit to the impurity capacity of the polycrystalline layer, and it is quite impossible to put this idea into practice. It might be thought that one could make the polycrystalline layer thicker. However, in the above-mentioned direct contact method, the gate electrode layer has the same thickness as that of the interconnecting wiring layer so that there results the problem referred to as "side etch phenomenon" at the gate electrode in accordance with the thickness of the gate electrode layer in a manufacturing process as shown in FIG. 1. Generally the forming of a gate electrode layer 10 in the predetermined pattern is made using an etching means, for instance, in a fluorine plasma with the photoresist film 11 as a mask. When this is done, the etching produces a lateral direction etch C (side etch) of which the amount is approximately the same as the etch amount B in the longitudinal direction. Because of this, the dimension of the polycrystalline silicon layer that is formed becomes smaller than the mask dimensions by about twice the film thickness (2B=2C). Furthermore in a manufacturing line, in practice, variations in the polycrystalline layer thickness, variations in the etching rate and the like occur, and therefore the finished dimensions actually vary greatly, which cause variations in the mutual conductance and the threshold voltage characteristics of each MOS transistor. For these reasons, it is desirable to make the gate electrode layer thin. However in the well-known direct contact method, the gate electrode layer and interconnecting wiring layer are formed in a body that, it is impossible to reduce the resistance of the interconnecting wiring and simultaneously minimize the side etch of the gate electrode layer.